1. Field of Invention
The present invention relates to a structure of an integrated circuit (IC) and a fabrication method thereof. More particularly, the present invention relates to a read only memory device that comprises a high dielectric constant (high-K) tunneling dielectric layer and a fabrication method thereof.
2. Description of Related Art
With the advances in miniature processing technology in a semiconductor manufacturing process, the miniaturization of a device dimension provides an increase of integration of semiconductor device, an enhancement of the function of integrated circuit, a lowering of cost, an improvement of the devices replacement rate and a lowering of the devices consumption rate. Accompany with the reduction of the dimension of a semiconductor device, the thickness of the dielectric layer (oxide layer) between the gate and the substrate needs to become thinner in order to maintain the capacitance between the gate and the channel.
For a programmable and erasable read only memory device, silicon dioxide formed by thermal oxidation is typically used to form the tunnel oxide layer. Therefore, as the device dimension for a read only memory device continues to reduce, the thickness for the tunnel oxide layer must become thinner accordingly. However, the tunnel oxide layer comprises a low limit in thickness. In other words, the tunnel oxide layer must comprise a certain thickness. When the thickness of the tunnel oxide layer is below the lower limit, many problems will surface. For example, during a subsequent thermal process, a thin tunnel oxide layer cannot prevent oxygen or dopants to diffuse into the substrate or to be trapped in the tunnel oxide layer, thereby changing the device's threshold voltage. Further, when the thickness of the tunnel oxide layer is smaller than the lower limit, the retention property of the tunnel oxide layer will become inferior. Consequently, the electrons that are stored in the charge trapping layer will flow into the substrate through the tunnel oxide layer. Losing the stored information and generation of current leakage are thereby resulted. Therefore, as indicated in the above, limited by the thickness of the tunnel oxide layer, the read only memory device dimension cannot be reduced further.